We are seeking a Verilog Writer / RTL Design Engineer for a full-time role based in the Philippines. The position focuses on RTL design and coding, simulation and testbench development, and work within FPGA or ASIC design flows. Compensation is USD $18,000 per year.Key ResponsibilitiesWrite RTL using Verilog and SystemVerilog.Develop RTL designs and code.Develop simulations and testbenches.Work with FPGA or ASIC design flows.Required QualificationsBachelor’s degree in electrical engineering, computer engineering, or a related field, or equivalent experience.Knowledge of Verilog and SystemVerilog.Skills in RTL design and coding.Experience with simulation and testbench development.Familiarity with FPGA or ASIC design flows.