We are seeking a Verification Engineer to join our team in Melbourne, Florida. The ideal candidate will play a critical role in ensuring the reliability and performance of our verification processes within the engineering team.Key ResponsibilitiesDesign and implement verification environments using SystemVerilog to support FPGA verification.Conduct lab testing to validate hardware and software interactively.Utilize Universal Verification Methodology (UVM) for developing testbenches and checking mechanisms.Collaborate with cross-functional teams to ensure robust design verification processes.Analyze verification results and report findings to stakeholders, recommending improvements where necessary.Maintain thorough documentation of the verification procedures and results.Participate in project planning and the development lifecycle to drive timely deliverables.Required and preferred qualificationsBachelor's degree in a STEM field.Expert level proficiency in SystemVerilog and FPGA verification.Experience with UVM methodology.Relevant experience in lab testing and verification processes.Successful candidates will thrive in a technical environment that emphasizes collaboration and quality. Familiarity with industry-standard tools relevant to verification will be beneficial.This position involves interaction with various technical and managerial teams, facilitating effective communication and alignment on project goals.Verification Engineers will report to the Engineering Manager and will work closely with both hardware and software teams to ensure seamless integration and functionality of products.We encourage you to apply if you are passionate about verification engineering and eager to contribute towards innovative solutions in the tech industry.